
/*------------------- include --------------------*/

/*---------------------------------------------*/



module tb_cbb_rom; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000/25.0;  // 25MHz
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb_cbb_rom);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

reg [1:0] address ;
cbb_rom #(
    .MEM_FILE ("./tb/rom.hex"),  // ROM初始化文件 
    .MEM_NUM  (4) ,// ROM存储的数量
    .DATA_WIDTH (8) , //数据位宽
    .ENABLE_ASYNC (1)  // 是否异步于时钟输出
) u_cbb_rom (
    .clk( clk) , 
    .address ( address),
    .data_out( ) 
);



initial begin
    $display(" -------- cbb_rom sim ----------");
    rst_n = 0;
    address = 0 ;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(10) @(posedge clk) ;

    repeat(7) begin
        @(posedge clk) begin 
            address <= address + 1;
        end  
    end 

    repeat(10) @(posedge clk) ;
    $display("%d",$clog2(4));
    $display("done!");
	$dumpflush;
	$finish;
	$stop;	
end


// task push(input [7:0] d);
//     // input [7:0] d ; 
//     @(posedge clk) begin we <= 1 ; din <= d;   end
// endtask 



endmodule